1. Field of the Invention
The present invention generally relates to the field of electronic circuits. More specifically, the present invention relates to a method and apparatus for passing data across an asynchronous clock boundary.
2. Background Information
With advances in integrated circuit, microprocessor, networking and communication technologies, an increasing number of devices, in particular, digital computing devices, are being networked together. Such devices are often first coupled to a local area network, such as an Ethernet based office/home network. In turn, the local area networks are interconnected together through wide area networks, such as ATM networks, Frame Relays, and the TCP/IP based global inter-networks, Internet. In transmitting from one network to another, data typically flows through one or more devices functioning e.g. as a network bridge or router. During the transition between such devices, and even between components within a single device, data will often be driven by multiple asynchronous clock signals regulating the respective traffic flows.
Depending upon how the clocks vary with respect to one another, there is the risk that invalid data may be passed from one time domain to the next. More specifically, there may be a point in time when the second clock samples data as it is transitioning in accordance with the transition of the first clock. If two asynchronous clocks are operating at the same frequency but vary in phase, it is possible to align the clocks to be synchronous by adjusting the phase of one or both clocks. If, however, two asynchronous clocks are operating at different frequencies, the respective clock edges may drift relative to each other in non-integer multiples resulting in unpredictable and perhaps invalid data.
FIG. 1 is a timing diagram generated in accordance with the prior art illustrating the relationship between two asynchronous clock signals and a data signal to be passed from the first time domain to the second. As shown in FIG. 1, the data transitions at point (10b-10b)  (10b-14b) corresponding to the rising edges (10a-14a) of CLOCK A. Between each of these transition points the data is considered to be stable and valid. Clock B represents a clock signal from a second time domain operating asynchronously to CLOCK A. Each rising edge of clock signal B defines one of the eight time intervals indicated by dotted lines in FIG. 1. That is, each of the time intervals corresponds to one period of CLOCK B. If the data were to be sampled at clock interval t2, the data would be deemed stable resulting in valid data being returned. However, if the data were sampled at time interval t1 and/or t6, the data would be deemed unpredictable since the respective time intervals correspond to transition points of the data (e.g. 10b and 13b).
Although asynchronous buffers (e.g. FIFO) with separate read and write clocks have traditionally been utilized to transfer multi-bit data from one time domain to another, it is difficult to design a circuit to accurately handle multi-bit data transfers/transitions commonplace in today's high-speed networks and computing devices without such buffers. Therefore, a novel technique to pass data between time domains while overcoming the limitations of the prior art is desired.